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FPGA/TCL 에러 로그

ERROR: [Xicom 50-8] xicom

ERROR: [Xicom 50-8] xicom: Device:0, user chain number:1, slave index:3. Reading intermittently wrong data from core. Try slower target speed. Make sure design meets timing requirements.
ERROR: [Xicom 50-38] xicom: Device:0, user chain number:1, slave index:3, is not a valid CseXsdb Slave core.
ERROR: [Labtools 27-3176] hw_server failed during internal command.
Resolution: Check that the hw_server is running and the hardware connectivity to the target

 

This means the clock connected to the cl_debug_bridge module is slower than the required minimum of 78.125MHz. Please choose a faster clock to connect to your cl_debug_bridge.

 

 

Reference: https://github.com/aws/aws-fpga/blob/master/hdk/docs/Virtual_JTAG_XVC.md